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BDM interface construction
Status
Who is working on the BDM?
The Rockbox project has bought a P&E Wiggler, and LinusNielsenFeltzing has connected it to both H100 and H300. Documentation on the wiggler in Microsoft Word format: P&E BDM connection 2005-08-24: Newsflash! The H300 BDM interface is working!!!linus@linus:~/rockbox-all/iriver$ ./d GNU gdb 6.1.1 Copyright 2004 Free Software Foundation, Inc. GDB is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. Type "show copying" to see the conditions. There is absolutely no warranty for GDB. Type "show warranty" for details. This GDB was configured as "--host=i686-pc-linux-gnu --target=m68k-bdm-elf"... trying kernel driver: /dev/bdmcf0 trying bdm server: localhost:/dev/bdmcf0 Detected V2 core Coldfire debug module version is 0 (5206(e)/5272/5282) (gdb)2004-10-01: Newsflash! The BDM interface is working!!!
linus:/home/linus/iriver/build-bdm> m68k-bdm-elf-gdb GNU gdb 6.1.1 Copyright 2004 Free Software Foundation, Inc. GDB is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. Type "show copying" to see the conditions. There is absolutely no warranty for GDB. Type "show warranty" for details. This GDB was configured as "--host=i686-pc-linux-gnu --target=m68k-bdm-elf". (gdb) target bdm /dev/bdmcf3 CPU type: 1 Interface type: 1 Status 0x2 Driver version: 2.c CPU type: 1 Write system register TDR: 0x40000000 Read system register CSR: 0x1000000 Read system register RPC: 0x1260 Read system register VBR: 0x358 Read system register MBAR: 0x40000000 Detected V2 core Set delay 0 GDB target bdm connected to /dev/bdmcf3 Coldfire debug module version is 0 (5206(e)/5272/5282) (gdb)DaveHooper: Am I right in thinking the coldfire bdm support in gdb does not actually support the registers of the 5249 (MBAR2, RAMBAR2, ...)? I guess those are not so important but that's something else that probably needs addressing at some point (and giving back to the community) LinusNielsenFeltzing: Correct. It doesn't have support for the 5249 control registers. Some day, I might send them a patch...
Connectors
StephanNielsen: P&E Wiggler Pinout (which also corresponds to the Motorola recommended BDM pinout in the User's Manual p.178)  |
Clarification regarding the TEA/TA signal
The TEA signal in the BDM connector is used for terminating a hung bus access, i.e a bus error. The 68xxx family has a TEA signal to terminate a bus cycle when TA isn't asserted by the Chip Select logic. This generates a Bus Error on the 68xxx family. However, the 5249 doesn't have a TEA signal. Instead, the watchdog timer (SWT) takes care of the bus termination by asserting TA if the software doesn't respond to the IACK cycle of the watchdog timer interrupt. The debugger has to be able to terminate a hung bus cycle. It does so by asserting the TEA/TA signal, which generates a bus error on the 68xxx and terminates the bus cycle normally on the 5249.Debugging with BDM/GDB
This is not exactly for the MFC5249, but it may still help: Using gdb/bdm for hardware testing a 5272 boardLinks
MCF5206e BDM design: http://www.fortunecity.com/campus/psychology/493/bdm/bdm.htm (broken link, Google cache is still available)This "article" is based on this BDM design which seems like a good design for fast-speed BDM: http://www.cvs.cx/Documents/CFPOD.pdf Chip used in this design is a 20-pin PALCE16V8-25LNC Flash Erasable, Reprogrammable CMOS PAL Device. Can anyone confirm if it will work for the Coldfire 5249? The old Pisa BDM for m683xx: (will not work on the Coldfire, but contains interesting info anyway) Addtional BDM info: ftp://ftp.cybertec.com.au/pub/bdm/ , http://sourceforge.net/projects/bdm/
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Revision r1.20 - 24 Aug 2005 - 21:05 GMT - LinusNielsenFeltzing Parents: IriverPort |
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